The present invention relates to photolithography and more particularly to optical proximity correction methods used during the development of photolithography masks for use in lithographic apparatus comprising:
a radiation system for supplying a projection beam of radiation;
a support structure for supporting patterning means, the patterning means serving to pattern the projection beam according to a desired pattern;
a substrate table for holding a substrate; and
a projection system for projecting the patterned beam onto a target portion of the substrate.
The term xe2x80x9cpatterning meansxe2x80x9d as here employed should be broadly interpreted as referring to means that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate; the term xe2x80x9clight valvexe2x80x9d can also be used in this context. Generally, the said pattern will correspond to a particular functional layer in a device being created in the target portion, such as an integrated circuit or other device (see below). Examples of such patterning means include:
A mask. The concept of a mask is well known in lithography, and it includes mask types such as binary, alternating phase-shift, and attenuated phase-shift, as well as various hybrid mask types. Placement of such a mask in the radiation beam causes selective transmission (in the case of a transmissive mask) or reflection (in the case of a reflective mask) of the radiation impinging on the mask, according to the pattern on the mask. In the case of a mask, the support structure will generally be a mask table, which ensures that the mask can be held at a desired position in the incoming radiation beam, and that it can be moved relative to the beam if so desired.
A programmable mirror array. One example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident light as diffracted light, whereas unaddressed areas reflect incident light as undiffracted light. Using an appropriate filter, the said undiffracted light can be filtered out of the reflected beam, leaving only the diffracted light behind; in this manner, the beam becomes patterned according to the addressing pattern of the matrix-addressable surface. An alternative embodiment of a programmable mirror array employs a matrix arrangement of tiny mirrors, each of which can be individually tilted about an axis by applying a suitable localized electric field, or by employing piezoelectric actuation means. Once again, the mirrors are matrix-addressable, such that addressed mirrors will reflect an incoming radiation beam in a different direction to unaddressed mirrors; in this manner, the reflected beam is patterned according to the addressing pattern of the matrix-addressable mirrors. The required matrix addressing can be performed using suitable electronic means. In both of the situations described hereabove, the patterning means can comprise one or more programmable mirror arrays. More information on mirror arrays as here referred to can be gleaned, for example, from United States Patents U.S. Pat. No. 5,296,891 and U.S. Pat. No. 5,523,193, and PCT patent applications WO 98/38597 and WO 98/33096, which are incorporated herein by reference. In the case of a programmable mirror array, the said support structure may be embodied as a frame or table, for example, which may be fixed or movable as required.
A programmable LCD array. An example of such a construction is given in United States Patent U.S. Pat. No. 5,229,872, which is incorporated herein by reference. As above, the support structure in this case may be embodied as a frame or table, for example, which may be fixed or movable as required.
For purposes of simplicity, the rest of this text may, at certain locations, specifically direct itself to examples involving a mask and mask table; however, the general principles discussed in such instances should be seen in the broader context of the patterning means as hereabove set forth.
Lithographic projection apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the patterning means may generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In current apparatus, employing patterning by a mask on a mask table, a distinction can be made between two different types of machine. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatusxe2x80x94commonly referred to as a step-and-scan apparatusxe2x80x94each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the xe2x80x9cscanningxe2x80x9d direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally  less than 1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a pattern (e.g. in a mask) is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book xe2x80x9cMicrochip Fabrication: A Practical Guide to Semiconductor Processingxe2x80x9d, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
For the sake of simplicity, the projection system may hereinafter be referred to as the xe2x80x9clensxe2x80x9d; however, this term should be broadly interpreted as encompassing various types of projection system, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a xe2x80x9clensxe2x80x9d. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such xe2x80x9cmultiple stagexe2x80x9d devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Dual stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
As semiconductor manufacturing technology is quickly pushing towards the limits of optical lithography, the state-of-the-art processes to date have regularly produced ICs with features exhibiting critical dimensions (xe2x80x9cCDsxe2x80x9d) which are below the exposure wavelength (xe2x80x9cxcexxe2x80x9d). A xe2x80x9ccritical dimensionxe2x80x9d of a circuit is defined as the smallest width of a feature or the smallest space between two features. For feature patterns that are designed to be smaller than xcex, it has been recognized that the optical proximity effect (OPE) becomes much more severe, and in fact becomes intolerable for leading edge sub-xcex production processes.
Optical proximity effects are a well known characteristic of optical projection exposure tools. More specifically, proximity effects occur when very closely spaced circuit patterns are lithographically transferred to a resist layer on a wafer. The light waves of the closely spaced circuit features interact, thereby distorting the final transferred pattern features. In other words, diffraction causes adjacent features to interact with each other in such a way as to produce pattern dependent variations. The magnitude of the OPE on a given feature depends on the feature""s placement on the mask with respect to other features.
One of the primary problems caused by such proximity effects is an undesirable variation in feature CDs. For any leading edge semiconductor process, achieving tight control over the CDs of the features (i.e., circuit elements and interconnects) is typically the primary manufacturing goal, since this has a direct impact on wafer sort yield and speed-binning of the final product.
It has been known that the variations in the CDs of circuit features caused by OPE can be reduced by several methods. One such technique involves adjusting the illumination characteristics of the exposure tool. More specifically, by carefully selecting the ratio of the numerical aperture of the illumination condenser (xe2x80x9cNAcxe2x80x9d) to the numerical aperture of the imaging objective lens (xe2x80x9cNAoxe2x80x9d) (this ratio has been referred to as the partial coherence ratio-"sgr"), the degree of OPE can be manipulated to some extent.
In addition to using relatively incoherent illumination, such as described above, OPE can also be compensated for by xe2x80x9cpre-correctingxe2x80x9d the mask features. This family of techniques is generally known as optical proximity correction (OPC) techniques.
For example, in U.S. Pat. No. 5,242,770 (the ""770 patent), which is hereby incorporated by reference, the method of using scattering bars (SBs) for OPC is described. The ""770 patent demonstrates that the SB method is very effective for modifying isolated features so that the features behave as if the features are dense features. In so doing, the depth of focus (DOF) for the isolated features is also improved, thereby significantly increasing process latitude. Scattering bars (also known as intensity leveling bars or assist bars) are correction features (typically non-resolvable by the exposure tool) that are placed next to isolated feature edges on a mask in order to adjust the edge intensity gradients of the isolated edges. Preferably, the adjusted edge intensity gradients of the isolated edges match the edge intensity gradients of the dense feature edges, thereby causing the SB-assisted isolated features to have nearly the same width as densely nested features.
It is generally understood that the process latitude associated with dense structures is better than that associated with isolated structures under conventional illumination for large feature sizes. However, recently, more aggressive illumination schemes such as annular illumination and multipole illumination have been implemented as a means of improving resolution and known OPC techniques have not always had the desired effects with such illumination schemes.
An object of the invention is to provide a method for optimizing mask patterns for use with various different illumination schemes.
Accordingly, the present invention provides a method and technique for identifying and eliminating forbidden pitch regions, which degrade the overall printing performance, so as to allow for an improvement of the CDs and process latitude obtainable utilizing currently known photolithography tools and techniques. The xe2x80x9cforbidden pitchxe2x80x9d regions are regions in which both the critical dimension of the feature and the process latitude of the feature are negatively affected.
When utilizing such illumination schemes, the inventors of the present invention have noted that some optical phenomenon have become more prominent. In particular, the inventors have noticed a forbidden pitch phenomena. More specifically, there are pitch ranges within which the process latitude of a xe2x80x9cdensely locatedxe2x80x9d main feature, especially the exposure latitude, is worse than that of an isolated feature of the same size. This important observation indicates that the existence of the neighboring feature is not always beneficial for main feature printing, which is in contradiction to what is commonly conceived, prior to the discovery by the present inventors. Indeed, the present inventors believe that the forbidden pitch phenomenon has become a limiting factor in advanced photolithography. As such, suppressing the forbidden pitch phenomenon will be necessary to further improve the CDs and process latitude obtainable utilizing currently known semiconductor device manufacturing tools and techniques.
More specifically, the present invention relates to a method of identifying undesirable pitches between features when designing an integrated circuit (or other device) to be formed on a substrate by use of a lithographic exposure tool. In an exemplary embodiment, the method comprises the steps of (a) identifying extreme interaction pitch regions by determining illumination intensity levels for a given illumination angle over a range of pitches; and (b) identifying the undesirable pitches for each extreme interaction pitch region identified in step (a) by determining illumination intensities for a given extreme interaction pitch region over a range of illumination angles.
In accordance with the present invention, it is shown that the variation of the critical dimension as well as the process latitude of a main feature is a direct consequence of light field interference between the main feature and the neighboring features. Depending on the phase of the field produced by the neighboring features, the main feature critical dimension and process latitude can be improved by constructive light field interference, or degraded by destructive light field interference. The phase of the field produced by the neighboring features can be shown to be dependent on the pitch as well as the illumination angle. For a given illumination angle, the forbidden pitch lies in the location where the field produced by the neighboring features interferes with the field of the main feature destructively. The present invention provides a method for identifying the forbidden pitch regions (i.e., locations) for any feature size and any illumination condition. More importantly, the present invention provides a method for performing illumination design in order to suppress the forbidden pitch phenomena, thereby suppressing the negative effects associated therewith. In addition, the present invention provides for a method for utilizing scattering bar placement in conjunction with the suppression of the forbidden pitch phenomena to further minimize optical proximity effects and optimize overall printing performance.
As described in further detail below, the present invention provides significant advantages over the prior art. Most importantly, the present invention provides for identifying and eliminating forbidden pitch regions, which degrade the overall printing performance, thereby allowing for an improvement of the CDs and process latitude obtainable utilizing currently known photolithography tools and techniques.
It will be appreciated that in the present invention, the xe2x80x9cmask patternxe2x80x9d may be embodied in a mask but may also be applied using another type of patterning means, examples of which are mentioned above. The term xe2x80x9cmask patternxe2x80x9d is used herein for convenience but should not be construed as requiring the presence of a mask, unless the context otherwise requires.
Although specific reference may be made in this text to the use of the apparatus according to the invention in the manufacture of ICs, it should be explicitly understood that such an apparatus has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms xe2x80x9creticlexe2x80x9d, xe2x80x9cwaferxe2x80x9d or xe2x80x9cdiexe2x80x9d in this text should be considered as being replaced by the more general terms xe2x80x9cmaskxe2x80x9d, xe2x80x9csubstratexe2x80x9d and xe2x80x9ctarget portionxe2x80x9d, respectively.
In the present document, the terms xe2x80x9cradiationxe2x80x9d and xe2x80x9cbeamxe2x80x9d are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g. with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultra-violet radiation, e.g. having a wavelength in the range 5-20 nm), as well as particle beams, such as ion beams or electron beams.
Additional advantages of the present invention will become apparent to those skilled in the art from the following detailed description of exemplary embodiments of the present invention.